Integrated circuits are formed on semiconductor silicon substrate wafers by a series of layering, patterning and doping steps. Patterning typically involves photolithography where a layer of photoresist is applied and then selectively removed in a masking step. This exposes those areas in the upper layer of the wafer which are to be removed or etched away.
Etching is done either using a wet chemical etch or a dry etching method. This disclosure concerns dry etching methods. The term "dry etching" is a collective definition for any of plasma etching, ion beam etching, reactive ion etching (RIE), magnetically enhanced ion etching (MIE), electrocyclotron resonance etching (ECR), and magnetically confined cyclotron resonance etching (MCR).
It is known that reducing wafer temperature during a dry etch (a) increases resist selectivity; (b) increases selectivity to other films; and (c) enhances sidewall passivation thereby preventing photoresist undercutting and promoting anisotropic etching. "Selectivity" is a term which defines the removal of the underlying material or film. The better the selectivity for a given material, the less that material will be etched under given etch conditions. "Sidewall passivation" is the combination of the reactive etchant material with the sidewalls of the opening of the substrate material as etching proceeds down into a desired layer. A film forms on these sidewalls which retards etching in the lateral direction, thereby producing substantially straight sidewalls. The film is removed in a later processing step after etching is completed.
It is therefore desirable in most dry etching processes to maintain the wafer at a temperature which is very low to maximize the above advantages. The lowest practical cooling temperature presently employed is around 20.degree. C. because of an effect commonly known as low temperature post etch deposit. This known phenomenon becomes a problem below 20.degree. C., and becomes very pronounced at temperatures of 0.degree. C. and below.
The deposit results from reaction byproducts which form from the etchant materials after power to the reactor has been shut off at the conclusion of the desired etch. When power to the reactor is cut, the front (exposed) side of the wafer will no longer be heated by plasma. Further, the etchant byproducts will no longer be receiving excitation from plasma state electron collisions. As such, conditions become very favorable for deposition of compounds from the gas phase onto the cooled wafer.
With some etchant materials, the reaction byproducts are a result of reaction of the etchant materials with one another which then merely condense onto the cold wafer surface when power is interrupted. With other etchants, the undesired deposits result from a reaction of the etchant material with the material on the substrate wafer upon the interruption of power. Both mechanisms are highly undesirable. The lower the temperature to which the backside of the wafer is cooled, the more favorable the conditions for this adverse deposition.
FIG. 1 is a microscopic perspective view of a silicon substrate wafer illustrating the effects of low temperature post etch deposit. There illustrated is a silicon wafer 10 after a low temperature etch has been completed. Wafer 10 includes a series of conductive runners 12, 14, 16, and 18. The upper layer of runners 12, 14, 16, and 18 includes a layer of photoresist 18a, 18b, 18c, and 18d respectively. The spaces between the runners have been etched away to define channels 22, 24 and 26. The mass of material represented by numeral 28 is an undesired post etch deposit. Such a condition was obtained, in a low temperature etch of SiO.sub.2 which is selective to silicon. Example conditions would be an etch in an Elechtrotech omega-II RIE reactor with the temperature beneath the wafer maintained at -10.degree. C.; a first etching step conducted at 102 mtorr, 140 watts, 80 sccm SF.sub.6, and 11 sccm Ar for 2 minutes and 45 seconds; followed by a second etching step at 110 mtorr, 100 watts, and 50 sccm Cl.sub.2 for 1 minute and 15 seconds.
One object of this invention is to prevent low temperature dry etch deposit on a semiconductor substrate wafer in order to enable lower temperature dry etching.